Semiconductor device with connecting structure and method for fabricating the same

ABSTRACT

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, and a first connecting structure including a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer. A top surface of the first connecting insulating layer, top surfaces of the plurality of first connecting contacts, and top surfaces of the plurality of first supporting contacts are substantially coplanar. Bottom surfaces of the plurality of first connecting contacts contact a top surface of the first semiconductor structure.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a methodfor fabricating the semiconductor device, and more particularly, to asemiconductor device with a connecting structure and a method forfabricating the semiconductor device with the connecting structure.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cellular telephones, digital cameras, andother electronic equipment. The dimensions of semiconductor devices arecontinuously being scaled down to meet the increasing demand ofcomputing ability. However, a variety of issues arise during thedown-scaling process, and such issues are continuously increasing inquantity and complexity. Therefore, challenges remain in achievingimproved quality, yield, performance, and reliability and reducedcomplexity.

This Discussion of the Background section is provided for backgroundinformation only. The statements in this Discussion of the Backgroundare not an admission that the subject matter disclosed in this sectionconstitutes prior art to the present disclosure, and no part of thisDiscussion of the Background section may be used as an admission thatany part of this application, including this Discussion of theBackground section, constitutes prior art to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a semiconductor deviceincluding a first semiconductor structure, and a first connectingstructure including a first connecting insulating layer positioned onthe first semiconductor structure, a plurality of first connectingcontacts positioned in the first connecting insulating layer, and aplurality of first supporting contacts positioned in the firstconnecting insulating layer. A top surface of the first connectinginsulating layer, top surfaces of the plurality of first connectingcontacts, and top surfaces of the plurality of first supporting contactsare substantially coplanar. Bottom surfaces of the plurality of firstconnecting contacts contact a top surface of the first semiconductorstructure.

In some embodiments, the plurality of first connecting contacts have athickness greater than a thickness of the plurality of first supportingcontacts.

In some embodiments, the first semiconductor structure includes a firstsubstrate positioned below the first connecting structure and a firstinterconnection structure positioned between the first substrate and thefirst connecting structure. The first connecting insulating layer ispositioned on the first interconnection structure.

In some embodiments, the first interconnection structure includes afirst insulating layer positioned on the first substrate and a pluralityof first conductive features positioned in the first insulating layer.The bottom surfaces of the first connecting contacts contact topsurfaces of the plurality of first conductive features coplanar with atop surface of the first insulating layer.

In some embodiments, a semiconductor device includes a secondsemiconductor structure positioned on the first connecting structure.The top surfaces of the plurality of first connecting contacts contact abottom surface of the second semiconductor structure.

In some embodiments, the second semiconductor structure includes asecond interconnection structure positioned on the first connectingstructure and a second substrate positioned on the secondinterconnection structure. The second interconnection structure includesa second insulating layer positioned on the first connecting structureand a plurality of second conductive features positioned in the secondinsulating layer. The top surfaces of the plurality of first connectingcontacts contact bottom surfaces of the plurality of second conductivefeatures coplanar with a bottom surface of the second insulating layer.

In some embodiments, the second interconnection structure includes aplurality of guard rings positioned in the second insulating layer.Bottom surfaces of the plurality of guard rings contact the top surfacesof the plurality of first supporting contacts.

In some embodiments, a semiconductor device includes a plurality offirst liners positioned on sidewalls of the plurality of firstconnecting contacts and the bottom surfaces of the plurality of firstconnecting contacts.

In some embodiments, a semiconductor device includes a first porouslayer positioned between the first connecting insulating layer and thesecond insulating layer, between the first connecting insulating layerand the plurality of first connecting contacts, and between the firstconnecting insulating layer and the plurality of first supportingcontacts. A porosity of the first porous layer is between about 25% andabout 100%.

In some embodiments, a semiconductor device includes a plurality offirst liners positioned between the first porous layer and the pluralityof first connecting contacts and between the first porous layer and thefirst supporting contacts.

In some embodiments, a semiconductor device includes a through substratevia positioned in the second substrate.

In some embodiments, the first connecting insulating layer includes afirst bottom insulating layer positioned on the top surface of the firstsemiconductor structure, a first middle insulating layer positioned onthe first bottom insulating layer, and a first top insulating layerpositioned on the first middle insulating layer. The plurality of firstconnecting contacts penetrate the first bottom insulating layer, thefirst middle insulating layer, and the first top insulating layer, andthe plurality of first supporting contacts are positioned in the firsttop insulating layer.

In some embodiments, a semiconductor device includes a second connectingstructure positioned on the first connecting structure, and a secondsemiconductor structure positioned on the second connecting structure.The second connecting structure includes a second connecting insulatinglayer positioned on the first connecting structure, a plurality ofsecond connecting contacts positioned in the second connectinginsulating layer, and a plurality of second supporting contactspositioned in the second connecting insulating layer. Bottom surfaces ofthe plurality of second connecting contacts contact the top surfaces ofthe plurality of first connecting contacts.

In some embodiments, a cross-sectional profile of sidewalls of theplurality of first connecting contacts is slanted.

Another aspect of the present disclosure provides a method forfabricating a semiconductor device including providing a firstsemiconductor structure, and forming a first connecting structureincluding a first connecting insulating layer on the first semiconductorstructure, a plurality of first connecting contacts in the firstconnecting insulating layer, and a plurality of first supportingcontacts in the first connecting insulating layer.

In some embodiments, the first connecting insulating layer includes afirst bottom insulating layer formed on the first semiconductorstructure, a first middle insulating layer formed on the first bottominsulating layer, and a first top insulating layer formed on the firstmiddle insulating layer. The plurality of first connecting contactspenetrate the first top insulating layer, the first middle insulatinglayer, and the first bottom insulating layer, and the plurality of firstsupporting contacts are formed in the first top insulating layer.

In some embodiments, a method for fabricating a semiconductor deviceincludes forming a layer of an energy-removable material on a topsurface of the first connecting insulating layer, between the pluralityof first connecting contacts and the first connecting insulating layer,and between the plurality of first supporting contacts and the firstconnecting insulating layer, and performing an energy treatment to turnthe layer of energy-removable material into a first porous layer. Aporosity of the first porous layer is between about 25% and about 100%.

In some embodiments, the energy-removable material includes a basematerial and a decomposable porogen material.

In some embodiments, the base material includes methylsilsesquioxane,low-dielectric materials, or silicon oxide.

In some embodiments, an energy source of the energy treatment is heat,light, or a combination thereof.

Due to the design of the semiconductor device of the present disclosure,multiple semiconductor devices may be connected together through thefirst connecting structure to provide more sophisticated functionalitywhile occupying less volume. Therefore, the cost of the semiconductordevice may be reduced, and the profit of the semiconductor device may beincreased. In addition, the plurality of first supporting contacts mayimprove the bonding strength between the first connecting structure andthe multiple semiconductor structures.

The foregoing has outlined rather broadly the features and technicaladvantages of the present disclosure in order that the detaileddescription of the disclosure that follows may be better understood.Additional features and advantages of the disclosure will be describedhereinafter, and form the subject of the claims of the disclosure. Itshould be appreciated by those skilled in the art that the conceptionand specific embodiment disclosed may be readily utilized as a basis formodifying or designing other structures or processes for carrying outthe same purposes of the present disclosure. It should also be realizedby those skilled in the art that such equivalent constructions do notdepart from the spirit and scope of the disclosure as set forth in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates, in a schematic cross-sectional diagram, asemiconductor device in accordance with one embodiment of the presentdisclosure;

FIGS. 2 to 10 illustrate, in schematic cross-sectional diagrams,semiconductor devices in accordance with embodiments of the presentdisclosure;

FIG. 11 illustrates, in a flowchart diagram form a method forfabricating a semiconductor device in accordance with one embodiment ofthe present disclosure:

FIGS. 12 to 16 illustrate, in schematic cross-sectional view diagrams, aflow for fabricating the semiconductor device in accordance with oneembodiment of the present disclosure;

FIGS. 17 to 20 illustrate, in schematic cross-sectional view diagrams, aflow for fabricating a semiconductor device in accordance with anotherembodiment of the present disclosure;

FIGS. 21 to 23 illustrate, in schematic cross-sectional view diagrams, aflow for fabricating a semiconductor device in accordance with anotherembodiment of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

It should be understood that when an element or layer is referred to asbeing “connected to” or “coupled to” another element or layer, it can bedirectly connected to or coupled to another element or layer, orintervening elements or layers may be present.

It should be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. Unless indicated otherwise, these terms areonly used to distinguish one element from another element. Thus, forexample, a first element, a first component or a first section discussedbelow could be termed a second element, a second component or a secondsection without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, terms such as “same,” “equal,”“planar,” or “coplanar,” as used herein when referring to orientation,layout, location, shapes, sizes, amounts, or other measures, do notnecessarily mean an exactly identical orientation, layout, location,shape, size, amount, or other measure, but are intended to encompassnearly identical orientation, layout, location, shapes, sizes, amounts,or other measures within acceptable variations that may occur, forexample, due to manufacturing processes. The term “substantially” may beused herein to reflect this meaning. For example, items described as“substantially the same,” “substantially equal,” or “substantiallyplanar,” may be exactly the same, equal, or planar, or may be the same,equal, or planar within acceptable variations that may occur, forexample, due to manufacturing processes.

In the present disclosure, a semiconductor device generally means adevice which can function by utilizing semiconductor characteristics,and an electro-optic device, a light-emitting display device, asemiconductor circuit, and an electronic device are all included in thecategory of the semiconductor device.

It should be noted that, in the description of the present disclosure,above (or up) corresponds to the direction of the arrow of the directionZ, and below (or down) corresponds to the opposite direction of thearrow of the direction Z.

FIG. 1 illustrates, in a schematic cross-sectional diagram, asemiconductor device 10A in accordance with one embodiment of thepresent disclosure.

With reference to FIG. 1, the semiconductor device 10A may include afirst semiconductor structure 100, a second semiconductor structure 200,and a first connecting structure 400. The first semiconductor structure100 and the second semiconductor structure 200 may be a semiconductorwafer, a portion of a semiconductor wafer, or a semiconductor die. Inthe embodiment depicted, the first semiconductor structure 100 and thesecond semiconductor structure 200 are semiconductor dies. The firstsemiconductor structure 100 may include a first substrate 101 and afirst interconnection structure 103. The first interconnection structure103 may be disposed on the first substrate 101.

With reference to FIG. 1, the first substrate 101 may be formed of, forexample, silicon, silicon carbide, gennanium silicon germanium, galliumarsenic, indium arsenide, indium, or other semiconductor materialsincluding group III, group IV, and group V elements. In someembodiments, the first substrate 101 may include a silicon-on-insulatorstructure. For example, the first substrate 101 may include a buriedoxide layer formed by using a process such as separation by implantedoxygen.

With reference to FIG. 1, the first interconnection structure 103 mayinclude a first insulating layer 105, a plurality of device elements(not shown in FIG. 1 for clarity), and a plurality of first conductivefeatures. The first insulating layer 105 may be disposed on the firstsubstrate 101. In some embodiments, the first insulating layer 105 maybe a stacked layer structure. The first insulating layer 105 may includea plurality of first insulating sub-layers. Each of the plurality offirst insulating sub-layers may have a thickness between about 0.5micrometer and about 3.0 micrometer. The plurality of first insulatingsub-layers may be formed of, for example, silicon oxide,borophosphosilicate glass, undoped silicate glass, fluorinated silicateglass, low-k dielectric materials, the like, or a combination thereof.The plurality of first insulating sub-layers may be formed of differentmaterials, but are not limited thereto. The low-k dielectric materialsmay have a dielectric constant less than 3.0 or even less than 2.5. Insome embodiments, the low-k dielectric materials may have a dielectricconstant less than 2.0.

In some embodiments, the plurality of device elements may be disposed ina lower portion of the first insulating layer 105. The plurality ofdevice elements may be disposed on the first substrate 101. Theplurality of device elements may be, for example, bipolar junctiontransistors, metal-oxide-semiconductor field-effect transistors, diodes,system large-scale integration, flash memories, dynamic random-accessmemories, static random-access memories, electrically erasableprogrammable read-only memories, image sensors, micro-electro-mechanicalsystems, active devices, or passive devices. In some embodiments,portions of the device elements may be disposed in the first substrate101. For example, source/drain regions of a metal-oxide-semiconductorfield-effect transistor may be disposed in the first substrate 101. Insome embodiments, the device elements may be electrically insulated fromneighboring device elements by insulating structures such as shallowtrench isolations.

It should be noted that, in the description of the present disclosure, asurface of an element (or a feature) located at the highest verticallevel along the direction Z is referred to as a top surface of theelement (or the feature). A surface of an element (or a feature) locatedat the lowest vertical level along the direction Z is referred to as abottom surface of the element (or the feature).

With reference to FIG. 1, the plurality of first conductive features maybe disposed in the first insulating layer 105. The plurality of firstconductive features may include, for example, a plurality of firstconductive lines 107, a plurality of first conductive vias 109, and aplurality of first conductive contacts 111. The first conductive vias109 may connect adjacent conductive lines along the direction Z. Thefirst conductive vias 109 may improve heat dissipation in the firstinterconnection structure 103 and provide structural support to thefirst interconnection structure 103. In some embodiments, the pluralityof device elements may be interconnected through the plurality of firstconductive features. In some embodiments, some of the plurality of firstconductive features may include wider portions. The wider portions maybe referred to as first conductive pads. In some embodiments, aplurality of first barrier layers 113 may be disposed between theplurality of first conductive features and the first insulating layer105. Each of the plurality of first barrier layers 113 may coversidewalls and a bottom surface of a corresponding one of the pluralityof first conductive features. Some of the plurality of first barrierlayers 113 may be disposed between some of the plurality of firstconductive features. For example, one of the plurality of first barrierlayers 113 may be disposed between a first conductive line 107 and afirst conductive via 109 that are adjacent to each other.

With reference to FIG. 1, the first interconnection structure 103 mayinclude a plurality of first guard rings 115. The plurality of firstguard rings 115 may consist of some of the plurality of first conductivelines 107 and some of the plurality of first conductive vias 109electrically connected. The plurality of first guard rings 115 may bedummies. The plurality of first guard rings 115 may have a samethickness as a thickness of the first insulating layer 105. In otherwords, the plurality of first guard rings 115 may penetrate the firstinsulating layer 105 along the direction Z. The plurality of first guardrings 115 may facilitate the planarization process during the formationof the plurality of first conductive features. The plurality of firstguard rings 115 may also facilitate a bonding process with anotherstructure such as the first connecting structure 400 or the secondsemiconductor structure 200. Furthermore, the plurality of first guardrings 115 may improve the mechanical strength of the firstinterconnection structure 103. In some embodiments, the first guard ring115 may consist of some conductive lines 107 disposed along thedirection Z and apart from each other.

It should be noted that referring to an element as a “dummy” elementmeans the element is electrically insulated from all of the deviceelements. In addition, when the semiconductor device is in operation, noexterior voltage or current will apply to the element.

With reference to FIG. 1, the top surface of the first insulating layer105 and the top surfaces of some of the plurality of first conductivelines 107 may be substantially coplanar. In some embodiments, the topsurface of the first insulating layer 105, the top surfaces of some ofthe plurality of first conductive lines 107, and the top surfaces ofsome of the plurality of first guard rings 115 may be substantiallycoplanar. In some embodiments, the top surface of the first insulatinglayer 105, the top surfaces of some of the plurality of first conductivelines 107, the top surfaces of some of the plurality of first guardrings 115, and the top surfaces of some of the plurality of firstbarrier layers 113 may be substantially coplanar. The plane consistingof the top surface of the first insulating layer 105, the top surfacesof some of the plurality of first conductive lines 107, the top surfacesof some of the plurality of first guard rings 115, and the top surfacesof some of the plurality of first barrier layers 113 may be referred toas the top surface of the first interconnection structure 103.

In some embodiments, the bottom surfaces of some of the plurality offirst conductive contacts 111 and the bottom surface of the firstinsulating layer 105 may be substantially coplanar. In some embodiments,the bottom surfaces of some of the plurality of first conductivecontacts 111, the bottom surfaces of some other of the plurality offirst guard rings 115, the bottom surface of the first insulating layer105, and the top surface of the first substrate 101 may be substantiallycoplanar. The plane consisting of the bottom surfaces of some of theplurality of first conductive contacts 111, the bottom surfaces of someother of the plurality of first guard rings 115, and the bottom surfaceof the first insulating layer 105 may be referred to as the bottomsurface of the first interconnection structure 103.

The plurality of first conductive lines 107, the plurality of firstconductive vias 109, and the plurality of first conductive contacts 111may be formed of, for example, copper, aluminum, titanium, the like, ora combination thereof. The plurality of first conductive lines 107, theplurality of first conductive vias 109, and the plurality of firstconductive contacts 111 may be formed of different materials, but arenot limited thereto. The plurality of first barrier layers 113 may beformed of, for example, titanium nitride, tantalum nitride, titanium,tantalum, titanium tungsten, the like, or a combination thereof.

With reference to FIG. 1, the second semiconductor structure 200 may bedisposed opposite to the first semiconductor structure 100 with thefirst connecting structure 400 interposed therebetween. The firstsemiconductor structure 100 and the second semiconductor structure 200may provide different functionalities. For example, the firstsemiconductor structure 100 may provide a logic function and the secondsemiconductor structure 200 may provide a memory function. In someembodiments, the first semiconductor structure 100 and the secondsemiconductor structure 200 may provide the same functionality.

With reference to FIG. 1, the second semiconductor structure 200 mayinclude a second substrate 201, a second interconnection structure 203,a second through substrate via 217, second insulating sidewalls 219, asecond top passivation layer 223, a second redistribution layer 225, asecond under bump metallization layer 227, and a second conductive bump229.

With reference to FIG. 1, the second substrate 201 may be disposedopposite to the first connecting structure 400 with the secondinterconnection structure 203 interposed there between. The secondsubstrate 201 has a structure similar to that of the first substrate101, but is not limited thereto. The second substrate 201 may be formedof a same material as the first substrate 101, but is not limitedthereto. The second interconnection structure 203 may have a structuresimilar to that of the first interconnection structure 103, but is notlimited thereto. In the present embodiment, the second interconnectionstructure 203 may have a structure similar to that of the firstinterconnection structure 103 but may be placed in an upside-downmanner. The second interconnection structure 203 may include a secondinsulating layer 205, a plurality of device elements (not shown in FIG.1 for clarity), a plurality of second conductive features, a pluralityof second barrier layers 213, and a plurality of second guard rings 215.The plurality of device elements of the second semiconductor structure200 may be disposed adjacent to an upper portion of the secondinsulating layer 205.

With reference to FIG. 1, the plurality of second conductive featuresmay be disposed in the second insulating layer 205. The plurality ofsecond conductive features may include a plurality of second conductivelines 207, a plurality of second conductive vias 209, and a plurality ofsecond conductive contacts 211. The plurality of second guard rings 215may consist of some of the plurality of second conductive lines 207electrically connected to some of the plurality of second conductivevias 209. The plurality of second guard rings 215 may be dummies.

With reference to FIG. 1, the bottom surfaces of some of the pluralityof second conductive lines 207, the bottom surface of the secondinsulating layer 205, the bottom surfaces of some of the second guardrings 215, and the bottom surfaces of some of the plurality of secondbarrier layers 213 may be substantially coplanar. The plane consistingof the bottom surfaces of some of the plurality of second conductivelines 207, the bottom surface of the second insulating layer 205, thebottom surfaces of some of the second guard rings 215, and the bottomsurfaces of some of the plurality of second barrier layers 213 may bereferred to as the bottom surface of the second interconnectionstructure 203. The top surfaces of some of the plurality of secondconductive contacts 211, the top surfaces of some of the second guardrings 215, and the top surface of the second insulating layer 205 may besubstantially coplanar. The plane consisting of the top surfaces of someof the plurality of second conductive contacts 211, the top surfaces ofsome of the second guard rings 215, and the top surface of the secondinsulating layer 205 may be referred to as the top surface of the secondinterconnection structure 203.

With reference to FIG. 1, the second through substrate via 217 may bedisposed in the second substrate 201 and electrically connected to oneof the plurality of second conductive contacts 211. In some embodiments,the second through substrate via 217 may be electrically connected toone of the device elements of the first semiconductor structure 100through some of the plurality of second conductive features. In someembodiments, the second through substrate via 217 may be electricallyconnected to the first connecting structure 400 through some of theplurality of second conductive features. In some embodiments, the secondthrough substrate via 217 may not penetrate through the secondinsulating layer 205. In some embodiments, the second through substratevia 217 may not occupy excessive space of the second semiconductorstructure 200. Therefore, more device elements may be disposed in thesecond semiconductor structure 200 to provide a more sophisticatedsemiconductor device. The second through substrate via 217 may be formedof, for example, copper, aluminum, titanium, the like, or a combinationthereof.

With reference to FIG. 1, the second insulating sidewalls 219 may bedisposed on sidewalls of the second through substrate via 217. Thesecond insulating sidewalls 219 may electrically isolate the secondthrough substrate via 217 from neighboring conductive elements disposedadjacent to two sides of the second through substrate via 217. Thesecond bottom passivation layer 221 may be disposed on the secondsubstrate 201. The second top passivation layer 223 may be disposed onthe second bottom passivation layer 221. A second redistribution layer225 may be disposed in the second bottom passivation layer 221. Aportion of the second bottom passivation layer 221 and a portion of thesecond top passivation layer 223 may be recessed to expose a portion ofa top surface of the second redistribution layer 225. The second bottompassivation layer 221 and the second top passivation layer 223 may beformed of, for example, silicon nitride, silicon oxynitride, siliconoxide nitride, polyimide, polybenzoxazole, or a combination thereof. Thesecond bottom passivation layer 221 and the second top passivation layer223 may be formed of different materials, but are not limited thereto.The second redistribution layer 225 may be electrically connected to thesecond through substrate via 217. The second redistribution layer 225may be formed of, for example, tungsten, titanium, tin, nickel, copper,gold, aluminum, platinum, cobalt, or a combination thereof.

It should be noted that, in the present disclosure, silicon oxynitriderefers to a substance which contains silicon, nitrogen and oxygen and inwhich a proportion of oxygen is greater than that of nitrogen. Siliconnitride oxide refers to a substance which contains silicon, oxygen andnitrogen and in which a proportion of nitrogen is greater than that ofoxygen.

With reference to FIG. 1, the second under bump metallization layer 227may be disposed on the second top passivation layer 223 and the portionof the top surface of the second redistribution layer 225. The secondconductive bump 229 may be disposed on the second under bumpmetallization layer 227 and electrically connected to the secondredistribution layer 225. The second under bump metallization layer 227may be formed of, for example, chromium, tungsten, titanium, copper,nickel, aluminum, palladium, gold, vanadium, or a combination thereof.The second conductive bump 229 may be a solder bump.

The second under bump metallization layer 227 may be a single layerstructure or a stacked structure of multiple layers. For example, thesecond under bump metallization layer 227 may include a first conductivelayer, a second conductive layer, and a third conductive layer stackedsequentially. The first conductive layer may serve as an adhesive layerfor stably attaching the second conductive bump 229 to the secondredistribution layer 225 and the second top passivation layer 223. Forexample, the first conductive layer may include at least one oftitanium, titanium-tungsten, chromium, and aluminum. The secondconductive layer may serve as a barrier layer for preventing aconductive material contained in the second conductive bump 229 fromdiffusing into the second redistribution layer 225 or the second toppassivation layer 223. The second conductive layer may include at leastone of copper, nickel, chromium-copper, and nickel-vanadium. The thirdconductive layer may serve as a seed layer for forming the secondconductive bump 229 or as a wetting layer for improving wettingcharacteristics of the second conductive bump 229. The third conductivelayer may include at least one of nickel, copper, and aluminum.

With reference to FIG. 1, the first connecting structure 400 may bedisposed between the first semiconductor structure 100 and the secondsemiconductor structure 200. The first connecting structure 400 mayinclude a first connecting insulating layer 401, a plurality of firstconnecting contacts 409, a plurality of first supporting contacts 411,and a plurality of first liners 413. The first connecting insulatinglayer 401 may be disposed on the top surface of the firstinterconnection structure 103.

With reference to FIG. 1, the plurality of first connecting contacts 409and the plurality of first supporting contacts 411 may be disposed inthe first connecting insulating layer 401. The plurality of firstsupporting contacts 411 may be dummies. The plurality of firstconnecting contacts 409 may have a thickness greater than a thickness ofthe plurality of first supporting contacts 411. Top surfaces of theplurality of first connecting contacts 409 may contact or bond to thebottom surfaces of some of the plurality of second conductive lines 207coplanar with the bottom surface of the second interconnection structure203. The top surfaces of the plurality of first connecting contacts 409may have a width equal to or less than a width of the bottom surfaces ofsome of the plurality of second conductive lines 207 coplanar with thebottom surface of the second interconnection structure 203. Bottomsurfaces of the plurality of first connecting contacts 409 may contactor bond to the top surfaces of some of the plurality of first conductivelines 107 coplanar with the top surface of the first interconnectionstructure 103. The bottom surfaces of the plurality of first connectingcontacts 409 may have a width equal to or less than a width of the topsurfaces of some of the plurality of first conductive lines 107 coplanarwith the top surface of the first interconnection structure 103.

With reference to FIG. 1, top surfaces of the plurality of the firstsupporting contacts 411 may contact or bond to the bottom surfaces ofthe plurality of second guard rings 215 coplanar with the bottom surfaceof the second interconnection structure 203. In some embodiments, someof the top surfaces of the plurality of first supporting contacts 411may contact or bond to the bottom surfaces of the plurality of secondguard rings 215 coplanar with the bottom surface of the secondinterconnection structure 203. In some embodiments, the bottom surfacesof the plurality of first supporting contacts 411 may contact or bond tosome of the plurality of second guard rings 215 coplanar with the bottomsurface of the second interconnection structure 203.

In some embodiments, the plurality of first connecting contacts 409 maypenetrate the first connecting insulating layer 401 along the directionZ and electrically connect the device elements of the firstsemiconductor structure 100 and the device elements of the secondsemiconductor structure 200 through some of the plurality of firstconductive features and some of the plurality of second conductivefeatures. In some embodiments, the first connecting insulating layer 401may be a multi-layer structure including a first bottom insulating layer403, a first middle insulating layer 405, and a first top insulatinglayer 407. The first bottom insulating layer 403 may be disposed on thetop surface of the first interconnection structure 103. The first bottominsulating layer 403 may be an etch stop layer and may be formed of, forexample, silicon nitride, silicon carbide, silicon oxide, low-kdielectric materials, extremely low-k dielectric materials, the like, ora combination thereof. The low-k dielectric materials may be, forexample, carbon doped oxides. The extremely low-k dielectric materialsmay be, for example, porous carbon doped silicon oxide.

With reference to FIG. 1, the first middle insulating layer 405 may bedisposed on the first bottom insulating layer 403. The first topinsulating layer 407 may be disposed on the first middle insulatinglayer 405. The second interconnection structure 203 may be disposed onthe first top insulating layer 407. The first middle insulating layer405 and the first top insulating layer 407 may be formed of, forexample, silicon oxide, silicon oxynitride, silicon nitride,borosilicate glass, borophosphosilicate glass, phosphoric silicateglass, fluorinated silicate glass, low-k dielectric materials, or acombination thereof. The first middle insulating layer 405 and the firsttop insulating layer 407 may be formed of different materials, but arenot limited thereto. The plurality of first connecting contacts 409 andthe plurality of first supporting contacts 411 may be formed of forexample, aluminum, copper, tungsten, or cobalt.

With reference to FIG. 1, the plurality of first connecting contacts 409may penetrate the first top insulating layer 407, the first middleinsulating layer 405, and the first bottom insulating layer 403 alongthe direction Z. The plurality of the first supporting contacts 411 maypenetrate the first top insulating layer 407 along the direction Z. Insome embodiments, the plurality of first supporting contacts 411 maypenetrate the first top insulating layer 407 and an upper portion of thefirst middle insulating layer 405. The plurality of first supportingcontacts 411 may facilitate a bonding process with the secondsemiconductor structure 200.

With reference to FIG. 1, the plurality of first liners 413 may bedisposed on sidewalls of the plurality of first connecting contacts 409,bottom surfaces of the plurality of first connecting contacts 409,sidewalls of the plurality of first supporting contacts 411, and bottomsurfaces of the plurality of first supporting contacts 411. Theplurality of first liners 413 may be formed of, for example, titaniumnitride, tantalum nitride, titanium, tantalum, titanium tungsten, thelike, or a combination thereof.

With reference to FIG. 1, the top surfaces of the plurality of firstconnecting contacts 409, the top surfaces of the plurality of firstsupporting contacts 411, top surfaces of the plurality of first liners413, and a top surface of the first top insulating layer 407 may besubstantially coplanar. The plane consisting of the top surfaces of theplurality of first connecting contacts 409, the top surfaces of theplurality of first supporting contacts 411, the top surfaces of theplurality of first liners 413, and the top surface of the first topinsulating layer 407 may be referred to as the top surface of the firstconnecting structure 400.

FIGS. 2 to 10 illustrate, in schematic cross-sectional diagrams,semiconductor devices 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, and 10J inaccordance with embodiments of the present disclosure.

With reference to FIG. 2, in the semiconductor device 10B, a firstporous layer 415 may be disposed on a top surface of the first topinsulating layer 407, the sidewalls and the bottom surfaces of theplurality of first supporting contacts 411, and the sidewalls of theplurality of first connecting contacts 409. In some embodiments, theplurality of first liners 413 may be disposed between the first porouslayer 415 and the plurality of first connecting contacts 409 and betweenthe first porous layer 415 and the plurality of first supportingcontacts 411. The first porous layer 415 may be formed of anenergy-removable material, as will be illustrated later.

The first porous layer 415 may include a skeleton and a plurality ofempty spaces disposed throughout the skeleton. The plurality of emptyspaces may connect to each other and may be filled with air. Theskeleton may include, for example, silicon oxide, low-dielectricmaterials, or methylsilsesquioxane. The first porous layer 415 may havea porosity between 25% and 100%. It should be noted that, when theporosity is 100%, it means the first porous layer 415 includes only anempty space and the first porous layer 415 may be regarded as an airgap. In some embodiments, the porosity of the first porous layer 415 maybe between 45% and 95%. The plurality of empty spaces of the firstporous layer 415 may be filled with air. As a result, a dielectricconstant of the first porous layer 415 may be significantly lower than alayer formed of, for example, silicon oxide. Therefore, the first porouslayer 415 may significantly reduce the parasitic capacitance between theplurality of first connecting contacts 409 and the plurality of firstsupporting contacts 411. That is, the first porous layer 415 maysignificantly alleviate an interference effect between electricalsignals induced or applied to the first connecting structure 400.

The energy-removable material may include a material such as a thermaldecomposable material, a photonic decomposable material, an e-beamdecomposable material, or a combination thereof. For example, theenergy-removable material may include a base material and a decomposableporogen material that is sacrificially removed upon being exposed to anenergy source.

With reference to FIG. 3, in the semiconductor device 10C, the firstporous layer 415 may be only disposed on the top surface of the firsttop insulating layer 407. The first connecting insulating layer 401 anda layer of energy-removable material may be sequentially formed on thefirst interconnection structure 103. Subsequently, the plurality of thefirst connecting contacts 409, the plurality of first supportingcontacts 411, and the plurality of first liners 413 may be formed byperforming single or multiple iterations of a single or double damasceneprocess through patterning on the first porous layer 415.

With reference to FIG. 4, in the semiconductor device 10D, the sidewallsof the plurality of first connecting contacts 409 and the sidewalls ofthe plurality of first supporting contacts 411 may have a slantedcross-sectional profile. In some embodiments, a width of each of theplurality of first connecting contacts 409 or a width of each of theplurality of first supporting contacts 411 may gradually become widerfrom bottom to top along the direction Z. In some embodiments, each ofthe plurality of first connecting contacts 409 as a whole or each of theplurality of first supporting contacts 411 as a whole may have a uniformslope.

With reference to FIG. 5, in the semiconductor device 10E, the firstsemiconductor structure 100 may be placed in an upside-down manner. Thefirst connecting structure 400 may be disposed on the first substrate101. A plurality of first through substrate vias 117 may be disposed inthe first substrate 101. The plurality of first through substrate vias117 may electrically connect the plurality of the first connectingcontacts 409 to some of the plurality of first conductive contacts 111.A first bottom passivation layer 121 may be disposed below the firstinterconnection structure 103. The first bottom passivation layer 121may be formed of, for example, silicon nitride, silicon oxynitride,silicon oxide nitride, polyimide, polybenzoxazole, or a combinationthereof. The first semiconductor structure 100 and the secondsemiconductor structure 200 may be stacked in a face-to-back manner.

With reference to FIG. 6, in the semiconductor device 10F, a secondbottom passivation layer 221 may be disposed on the second substrate201. The second bottom passivation layer 221 may be formed of, forexample, silicon nitride, silicon oxynitride, silicon oxide nitride,polyimide, polybenzoxazole, or a combination thereof. A second padstructure 231 may penetrate the second bottom passivation layer 221, thesecond substrate 201, and an upper portion of the second interconnectionstructure 203. The second pad structure 231 may electrically connect toone of the plurality of second conductive lines 207.

With reference to FIG. 7, in the semiconductor device 10G, the secondsemiconductor structure 200 may be placed in a manner similar to that ofthe first semiconductor structure 100. The second substrate 201 may bedisposed on the first connecting structure 400. The second bottompassivation layer 221 may be disposed on the second interconnectionstructure 203. The second through substrate vias 217 may be disposed inthe second substrate 201. The second through substrate vias 217 mayelectrically connect some of the plurality of second conductive contacts211 to the plurality of the first connecting contacts 409. The firstsemiconductor structure 100 and the second semiconductor structure 200may be stacked in a back-to-face manner.

With reference to FIG. 8, in the semiconductor device 10H, the firstconnecting structure 400 may be placed in an upside-down manner. Thefirst top insulating layer 407 may be disposed on the firstinterconnection structure 103. The second interconnection structure 203may be disposed on the first bottom insulating layer 403. The bottomsurfaces of the plurality of first supporting contacts 411 may contactor bond to the top surfaces of the first guard rings 115.

With reference to FIG. 9, in the semiconductor device 10I, a secondconnecting structure 500 may be disposed between the secondsemiconductor structure 200 and the first connecting structure 400. Thesecond connecting structure 500 may have a structure similar with thefirst connecting structure 400 but is placed in an upside-down manner.The second connecting structure 500 may include a second connectinginsulating layer 501, a plurality of second connecting contacts 509, aplurality of second supporting contacts 511, and a plurality of secondliners 513. The second connecting insulating layer 501 may include asecond bottom insulating layer 503, a second middle insulating layer505, and a second top insulating layer 507. The second top insulatinglayer 507 may be disposed on the first connecting structure 400. Thesecond middle insulating layer 505 may be disposed on the second topinsulating layer 507. The second bottom insulating layer 503 may bedisposed on the second middle insulating layer 505 and may be an etchstop layer.

With reference to FIG. 9, the plurality of second connecting contacts509 may penetrate the second bottom insulating layer 503, the secondmiddle insulating layer 505, and the second top insulating layer 507.The plurality of second connecting contacts 509 may electrically connectthe some of the plurality of second conductive lines 207 to theplurality of first connecting contacts 409. The second supportingcontacts 511 may be disposed in the second bottom insulating layer 503.Bottom surfaces of the plurality of second supporting contacts 511 maycontact or bond to the top surfaces of the plurality of first supportingcontacts 411. The plurality of second liners 513 may be disposed betweenthe plurality of second connecting contacts 509 and the secondconnecting insulating layer 501, between the plurality of secondsupporting contacts 511 and the second connecting insulating layer 501,and between the plurality of second connecting contacts 509 and some ofthe plurality of second conductive lines 207.

With reference to FIG. 10, in the semiconductor device 10J, a secondporous layer 515 may be disposed on the bottom surface of the second topinsulating layer 507, the sidewalls and bottom surfaces of the pluralityof second supporting contacts 511, and the sidewalls of the plurality ofsecond connecting contacts 509. The second porous layer 515 may beformed of a same material as the first porous layer 415. The secondporous layer 515 may have a porosity between 25% and 100%. The secondporous layer 515 disposed on the bottom surface of the second topinsulating layer 507 and the first porous layer 415 disposed on the topsurface of the first top insulating layer 407 may contact or bond toeach other. In some embodiments, the first porous layer 415 may be onlydisposed on the top surface of the first top insulating layer 407 andthe second porous layer 515 may be only disposed on the bottom surfaceof the second top insulating layer 507.

It should be noted that the terms “forming,” “formed” and “form” maymean and include any method of creating, building, patterning,implanting, or depositing an element, a dopant or a material. Examplesof forming methods may include, but are not limited to, atomic layerdeposition, chemical vapor deposition, physical vapor deposition,sputtering, co-sputtering, spin coating, diffusing, depositing, growing,implantation, photolithography, dry etching and wet etching.

FIG. 11 illustrates, in a flowchart diagram form, a method 20 forfabricating a semiconductor device 10A in accordance with one embodimentof the present disclosure. FIGS. 13 to 16 illustrate, in schematiccross-sectional view diagrams, a flow for fabricating the semiconductordevice in accordance with one embodiment of the present disclosure.

With reference to FIGS. 11 and 12, at step S11, a first semiconductorstructure 100 may be provided. The first semiconductor structure 100 mayinclude a first substrate 101 and a first interconnection structure 103formed on the first substrate 101. The first interconnection structure103 may include a first insulating layer 105, a plurality of deviceelements, a plurality of first conductive features, a plurality of firstbarrier layers 113, and a plurality of first guard rings 115. Theplurality of device elements of the first semiconductor structure 100may be formed in a lower portion of the first insulating layer 105.Portions of some of the plurality of device elements may be formed in anupper portion of the first substrate 101. The plurality of firstconductive features, the plurality of first barrier layers 113, and theplurality of first guard rings 115 may be formed in the first insulatinglayer 105. The plurality of first conductive features may include, forexample, a plurality of first conductive lines 107, a plurality of firstconductive vias 109, and a plurality of first conductive contacts 111.Some of the plurality of first conductive lines 107, some of theplurality of first conductive vias 109, and some of the plurality offirst barrier layers 113 may together form the plurality of first guardrings 115. The plurality of device elements of the first semiconductorstructure 100 and the plurality of first conductive features may beelectrically connected.

With reference to FIGS. 11 and 13, at step S13, a first connectingstructure 400 may be formed on the first semiconductor structure 100.The first connecting structure 400 may include a first connectinginsulating layer 401, a plurality of first connecting contacts 409, aplurality of first supporting contacts 411, and a plurality of firstliners 413. The first connecting insulating layer 401 may include afirst bottom insulating layer 403, a first middle insulating layer 405,and a first top insulating layer 407. The first bottom insulating layer403, the first middle insulating layer 405, and the first top insulatinglayer 407 may be sequentially formed on the first interconnectionstructure 103.

A series of photolithography processes, etching processes, depositionprocesses, and planarization processes may be performed to form theplurality of first connecting contacts 409, the plurality of firstsupporting contacts 411, and the plurality of first liners 413. Theplurality of first connecting contacts 409 may be formed so as topenetrate the first top insulating layer 407, the first middleinsulating layer 405, and the first bottom insulating layer 403 and maybe electrically connected to some of the plurality of first conductivefeatures adjacent to a top surface of the first interconnectionstructure 103. The plurality of first supporting contacts 411 may beformed in the first top insulating layer 407. The plurality of firstliners 413 may be formed between the plurality of first connectingcontacts 409 and the first connecting insulating layer 401, between theplurality of first supporting contacts 411 and the first connectinginsulating layer 401, and between the plurality of first connectingcontacts 409 and the some of the plurality of first conductive featuresadjacent to a top surface of the first interconnection structure 103.

With reference to FIGS. 11, 14, and 15, at step S15, a secondsemiconductor structure 200 may be bonded to the first connectingstructure 400 through a bonding process. With reference to FIG. 14, asecond semiconductor structure 200 may be provided. The secondsemiconductor structure 200 may be formed by a procedure similar to thatused to form the first semiconductor structure 100, and may have astructure similar to that of the first semiconductor structure 100. Thesecond semiconductor structure 200 may be placed in an upside-downmanner. With reference to FIG. 15, the upside-down second semiconductorstructure 200 may be placed on the top surface of the first connectingstructure 400. A thermal treatment may be performed to achieve a hybridbonding between elements of the second semiconductor structure 200 andthe first connecting structure 400 for the bonding process. The hybridbonding may include an oxide-to-oxide bonding and a metal-to-metalbonding. The oxide-to-oxide bonding may originate from the bondingbetween the second insulating layer 205 and the first top insulatinglayer 407. The metal-to-metal bonding may originate from the bondingbetween the plurality of first connecting contacts 409 and some of theplurality of second conductive lines 207, and from the bonding betweenthe plurality of first supporting contacts 411 and the plurality ofsecond guard rings 215. A temperature of the bonding process may bebetween about 300° C. and about 450° C. A thinning process may beperformed on the second substrate 201 using an etching process, achemical polishing process, or a grinding process to reduce a thicknessof the second substrate 201.

With reference to FIGS. 11 and 16, at step S17, a second throughsubstrate via 217 and second insulating sidewalls 219 may be formed inthe second substrate 201 of the second semiconductor structure 200 and asecond bottom passivation layer 221, a second top passivation layer 223,a second redistribution layer 225, a second under bump metallizationlayer 227, and a second conductive bump 229 may be formed on the secondsubstrate 201 of the second semiconductor structure 200. The secondbottom passivation layer 221 and the second top passivation layer 223may be sequentially formed on the second substrate 201. The secondredistribution layer 225 may be formed in the second bottom passivationlayer 221. The second through substrate via 217 may be formed in thesecond substrate 201 and may electrically connect the secondredistribution layer 225 to one of the plurality of second conductivecontacts 211. A portion of the second bottom passivation layer 221 and aportion of the second top passivation layer 223 may be recessed to forman opening to expose a portion of a top surface of the secondredistribution layer 225. The second under bump metallization layer 227and the second conductive bump 229 may be sequentially formed in theopening.

FIGS. 17 to 20 illustrate, in schematic cross-sectional view diagrams, aflow for fabricating a semiconductor device 10B in accordance withanother one embodiment of the present disclosure.

With reference to FIG. 17, a layer of an energy-removable material 417may be formed on the top surface of the first top insulating layer 407,formed between the plurality of first connecting contacts 409 and thefirst connecting insulating layer 401, and formed between the pluralityof first supporting contacts 411 and the first connecting insulatinglayer 401. The energy-removable material 417 may include a material suchas a thermal decomposable material, a photonic decomposable material, ane-beam decomposable material, or a combination thereof. For example, theenergy-removable material 417 may include a base material and adecomposable porogen material that is sacrificially removed uponexposure to an energy source. The base material may include amethylsilsesquioxane based material. The decomposable porogen materialmay include a porogen organic compound that provides porosity to thebase material of the energy-removable material. After formation of thelayer of the energy-removable material 417, an energy treatment may beperformed on the intermediate semiconductor device in FIG. 17 byapplying the energy source thereto. The energy source may include heat,light, or a combination thereof. When heat is used as the energy source,a temperature of the energy treatment may be between about 800° C. andabout 900° C. When light is used as the energy source, an ultravioletlight may be applied. The energy treatment may remove the decomposableporogen material from the energy-removable material to generate emptyspaces (pores), with the base material remaining in place.

Alternatively, in another embodiment, the base material may be siliconoxide. The decomposable porogen material may include compounds includingunsaturated bonds such as double bonds or triple bonds. During theenergy treatment, the unsaturated bonds of the decomposable porogenmaterial may cross-link with silicon oxide of the base material. As aresult, the decomposable porogen material may shrink and generate emptyspaces, with the base material remaining in place. The empty spaces maybe filled with air so that a dielectric constant of the empty spaces maybe significantly low. In some embodiments, the base material may below-k dielectric materials.

In some embodiments, the energy-removable material 417 may include arelatively high concentration of the decomposable porogen material and arelatively low concentration of the base material, but is not limitedthereto. For example, the energy-removable material 417 may includeabout 75% or greater of the decomposable porogen material, and about 25%or less of the base material. In another example, the energy-removablematerial 417 may include about 95% or greater of the decomposableporogen material, and about 5% or less of the base material. In anotherexample, the energy-removable material 417 may include about 100% of thedecomposable porogen material, and no base material. In another example,the energy-removable material 417 may include about 45% or greater ofthe decomposable porogen material, and about 55% or less of the basematerial.

With reference to FIG. 18, after the energy treatment, the layer of theenergy-removable material 417 may turn into a first porous layer 415.The base material may turn into a skeleton of the first porous layer 415and the empty spaces may be distributed throughout the skeleton of thefirst porous layer 415. According to the composition of theenergy-removable material 417, the first porous layer 415 may have aporosity of 45%, 75%, 95%, or 100%. A planarization process, such aschemical mechanical polishing, may be performed after the energytreatment to provide a substantially flat surface for subsequentprocessing steps.

With reference to FIG. 19, during a bonding process between the firstconnecting structure 400 and the second semiconductor structure 200, thefirst porous layer 415 formed on the top surface of the first topinsulating layer 407 may be thinned due to its porous characteristic. Asa result, the top surfaces of the plurality of first connecting contacts409, the top surfaces of the plurality of first supporting contacts 411,and the top surfaces of the plurality of first liners 413 may form aplurality of protrusions (highlighted in FIG. 19 with dashed circles).The plurality of protrusions may prevent the metal-to-metal bonding fromdielectrically interfering with the first top insulating layer 407 orthe second insulating layer 205. Therefore, a more reliable bondingbetween the second semiconductor structure 200 and the first connectingstructure 400 may be achieved. With reference to FIG. 20, elements maybe formed with a procedure similar to that illustrated in FIG. 16.

FIGS. 21 to 23 illustrate, in schematic cross-sectional view diagrams, aflow for fabricating a semiconductor device 10H in accordance withanother embodiment of the present disclosure.

With reference to FIG. 21, a first semiconductor structure 100 and asecond semiconductor structure 200 may be formed in a procedure similarto that illustrated in FIG. 12. The first connecting structure 400 maybe formed on the second semiconductor structure 200 with a proceduresimilar to that illustrated in FIG. 13. Subsequently, the secondsemiconductor structure 200 and the first connecting structure 400 maybe placed in an upside-down manner and above the first semiconductorstructure 100.

With reference to FIG. 22, a bonding process may be performed to bondthe first connecting structure 400 to the first semiconductor structure100. A thermal treatment may be applied to the intermediatesemiconductor device in FIG. 22 to achieve the hybrid bonding of thefirst semiconductor structure 100 to the first connecting structure 400.With reference to FIG. 23, a second bottom passivation layer 221 may beformed on the second substrate 201. A second pad structure 231 may beformed so as to penetrate the second bottom passivation layer 221, thesecond substrate 201, and an upper portion of the second insulatinglayer 205. The second pad structure 231 may be electrically connected toone of the plurality of second conductive lines 207.

One aspect of the present disclosure provides a semiconductor deviceincluding a first semiconductor structure, and a first connectingstructure including a first connecting insulating layer positioned onthe first semiconductor structure, a plurality of first connectingcontacts positioned in the first connecting insulating layer, and aplurality of first supporting contacts positioned in the firstconnecting insulating layer. A top surface of the first connectinginsulating layer, top surfaces of the plurality of first connectingcontacts, and top surfaces of the plurality of first supporting contactsare substantially coplanar. Bottom surfaces of the plurality of firstconnecting contacts contact a top surface of the first semiconductorstructure.

Another aspect of the present disclosure provides a method forfabricating a semiconductor device including providing a firstsemiconductor structure, and forming a first connecting structureincluding a first connecting insulating layer on the first semiconductorstructure, a plurality of first connecting contacts in the firstconnecting insulating layer, and a plurality of first supportingcontacts in the first connecting insulating layer.

Due to the design of the semiconductor device of the present disclosure,the first semiconductor structure 100 and the second semiconductorstructure 200 may be connected together through the first connectingstructure 400 to provide more sophisticated functionality whileoccupying less volume. Therefore, the cost of the semiconductor devicemay be reduced, and the profit of the semiconductor device may beincreased. In addition, the plurality of first supporting contacts 411may improve the bonding strength between the first connecting structure400 and the first semiconductor structure 100 or the secondsemiconductor structure 200.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the spirit andscope of the disclosure as defined by the appended claims. For example,many of the processes discussed above can be implemented in differentmethodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present disclosure, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein, may be utilized according tothe present disclosure. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, and steps.

What is claimed is:
 1. A semiconductor device, comprising: a firstsemiconductor structure; and a first connecting structure comprising afirst connecting insulating layer positioned on the first semiconductorstructure, a plurality of first connecting contacts positioned in thefirst connecting insulating layer, and a plurality of first supportingcontacts positioned in the first connecting insulating layer; wherein atop surface of the first connecting insulating layer, top surfaces ofthe plurality of first connecting contacts, and top surfaces of theplurality of first supporting contacts are substantially coplanar;wherein bottom surfaces of the plurality of first connecting contactscontact a top surface of the first semiconductor structure.
 2. Thesemiconductor device of claim 1, wherein the plurality of firstconnecting contacts have a thickness greater than a thickness of theplurality of first supporting contacts.
 3. The semiconductor device ofclaim 2, wherein the first semiconductor structure comprises a firstsubstrate positioned below the first connecting structure and a firstinterconnection structure positioned between the first substrate and thefirst connecting structure, wherein the first connecting insulatinglayer is positioned on the first interconnection structure.
 4. Thesemiconductor device of claim 3, wherein the first interconnectionstructure comprises a first insulating layer positioned on the firstsubstrate and a plurality of first conductive features positioned in thefirst insulating layer, wherein the bottom surfaces of the firstconnecting contacts contact top surfaces of the plurality of firstconductive features coplanar with a top surface of the first insulatinglayer.
 5. The semiconductor device of claim 4, further comprising asecond semiconductor structure positioned on the first connectingstructure, wherein the top surfaces of the plurality of first connectingcontacts contact a bottom surface of the second semiconductor structure.6. The semiconductor device of claim 5, wherein the second semiconductorstructure comprises a second interconnection structure positioned on thefirst connecting structure and a second substrate positioned on thesecond interconnection structure, wherein the second interconnectionstructure comprises a second insulating layer positioned on the firstconnecting structure and a plurality of second conductive featurespositioned in the second insulating layer, wherein the top surfaces ofthe plurality of first connecting contacts contact bottom surfaces ofthe plurality of second conductive features coplanar with a bottomsurface of the second insulating layer.
 7. The semiconductor device ofclaim 6, wherein the second interconnection structure comprises aplurality of guard rings positioned in the second insulating layer,wherein bottom surfaces of the plurality of guard rings contact the topsurfaces of the plurality of first supporting contacts.
 8. Thesemiconductor device of claim 7, further comprising a plurality of firstliners positioned on sidewalls of the plurality of first connectingcontacts and the bottom surfaces of the plurality of first connectingcontacts.
 9. The semiconductor device of claim 7, further comprising afirst porous layer positioned between the first connecting insulatinglayer and the second insulating layer, between the first connectinginsulating layer and the plurality of first connecting contacts, andbetween the first connecting insulating layer and the plurality of firstsupporting contacts, wherein a porosity of the first porous layer isbetween about 25% and about 100%.
 10. The semiconductor device of claim9, further comprising a plurality of first liners positioned between thefirst porous layer and the plurality of first connecting contacts andbetween the first porous layer and the first supporting contacts. 11.The semiconductor device of claim 10, further comprising a throughsubstrate via positioned in the second substrate.
 12. The semiconductordevice of claim 1, wherein the first connecting insulating layercomprises a first bottom insulating layer positioned on the top surfaceof the first semiconductor structure, a first middle insulating layerpositioned on the first bottom insulating layer, and a first topinsulating layer positioned on the first middle insulating layer,wherein the plurality of first connecting contacts penetrate the firstbottom insulating layer, the first middle insulating layer, and thefirst top insulating layer, and the plurality of first supportingcontacts are positioned in the first top insulating layer.
 13. Thesemiconductor device of claim 2, further comprising a second connectingstructure positioned on the first connecting structure, and a secondsemiconductor structure positioned on the second connecting structure,wherein the second connecting structure comprises a second connectinginsulating layer positioned on the first connecting structure, aplurality of second connecting contacts positioned in the secondconnecting insulating layer, and a plurality of second supportingcontacts positioned in the second connecting insulating layer, whereinbottom surfaces of the plurality of second connecting contacts contactthe top surfaces of the plurality of first connecting contacts.
 14. Thesemiconductor device of claim 2, wherein a cross-sectional profile ofsidewalls of the plurality of first connecting contacts is slanted. 15.A method for fabricating a semiconductor device, comprising: providing afirst semiconductor structure; and forming a first connecting structurecomprising a first connecting insulating layer on the firstsemiconductor structure, a plurality of first connecting contacts in thefirst connecting insulating layer, and a plurality of first supportingcontacts in the first connecting insulating layer.
 16. The method forfabricating the semiconductor device of claim 15, wherein the firstconnecting insulating layer comprises a first bottom insulating layerformed on the first semiconductor structure, a first middle insulatinglayer formed on the first bottom insulating layer, and a first topinsulating layer formed on the first middle insulating layer, whereinthe plurality of first connecting contacts are formed so as to penetratethe first top insulating layer, the first middle insulating layer, andthe first bottom insulating layer and the plurality of first supportingcontacts are formed in the first top insulating layer.
 17. The methodfor fabricating the semiconductor device of claim 15, furthercomprising: forming a layer of an energy-removable material on a topsurface of the first connecting insulating layer, between the pluralityof first connecting contacts and the first connecting insulating layer,and between the plurality of first supporting contacts and the firstconnecting insulating layer; and performing an energy treatment to turnthe layer of energy-removable material into a first porous layer,wherein a porosity of the first porous layer is between about 25% andabout 100%.
 18. The method for fabricating the semiconductor device ofclaim 17, wherein the energy-removable material comprises a basematerial and a decomposable porogen material.
 19. The method forfabricating the semiconductor device of claim 18, wherein the basematerial comprises methylsilsesquioxane, low-dielectric materials, orsilicon oxide.
 20. The method for fabricating the semiconductor deviceof claim 19, wherein an energy source of the energy treatment is heat,light, or a combination thereof.